Sheridan College CS • Cloud Computing Specialization

Software Developer &
Creative Systems Builder

Hi, I'm Chen. My work bridges reliable AI research and hands-on systems engineering, with past projects ranging from specification compilers to physical interactive computing installations. Right now, I'm pursuing my thesis on AI reasoning and faithfulness. Alongside my research, I develop AI pipelines for an industry collaboration with StereoLOGIC under the direction of Professor Nick Sajadi from Sheridan College, turning enterprise process, and task-mining data into actionable efficiency and cost savings.

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Toronto, ON

Featured Project & Hardware Installation

🏆 Winner: Best Hardware Project — BearHacks 2026Physical Computing • Edge AI • Human-Robot Interaction

EchoBin — Autonomous Sassy Waste-Sorting Installation

Physical Edge Hardware Intervening at the Point of Disposal via Behavioral Nudges

Improper waste sorting is one of the easiest environmental problems to solve, yet municipal guidelines remain widely confusing. EchoBin is an autonomous physical computing installation built to intervene directly before mistakes happen. By pairing real-time computer vision with conversational speech synthesis, it inspects items on approach and uses humor and playful friction to actively educate users.

EXTERIOR SENSOR FACEHC-SR04 proximity eyes & wide-angle USB camera

CHASSIS & INTERNAL HARNESSRaspberry Pi 4, GPIO breadboard harness & stepper drive

Raspberry Pi 4Gemma Vision MultimodalElevenLabs Voice AIAsynchronous Worker Queue

Devpost ↗

BearHacks 2026 • Best Hardware Winner Full Case Study

🏆 Winner: Best Hardware Project — BearHacks 2026Physical Edge ComputingHuman-Robot Interaction

EchoBin: Autonomous Sassy Waste-Sorting

An interactive physical installation that stops mis-sorting before it happens. Built with a Raspberry Pi 4, computer vision, and speech synthesis, EchoBin inspects items on approach and uses behavioral friction, witty voice feedback, and a motorized lid-lock to educate users.

PIPELINE LATENCY< 800 ms

TRIGGER RANGE10 – 40 cm

VISION STACKGemma Multimodal

SPEECH ENGINEElevenLabs Voice

01. Installation Video & Hardware Showcase

Live Hackathon Prototype

EXTERIOR FACE

HC-SR04 ultrasonic eyes & wide-angle camera aperture.

INTERNAL HARNESS

Raspberry Pi 4, ULN2003 stepper driver, and breadboard wiring.

LIVE EVALUATION

Real-time user testing and conversational pushback on the floor.

💡 The Design "Why": Friction Over Signage

Most sustainability campaigns rely on static informational posters that people ignore during routine disposal. For international students and newcomers, navigating distinct municipal streams (landfill vs. organics vs. co-mingled recycling) creates decision fatigue.

We designed EchoBin to introduce physical and conversational friction. By locking the lid and verbally calling out mistakes with a sassy persona, the bin forces conscious re-evaluation. Humor was chosen deliberately: it disarms defensiveness and makes environmental correction an entertaining social moment rather than a sterile reprimand.

⚡ The Engineering "Process": Pipeline Concurrency

Migrating from laptop mockups to a headless Raspberry Pi introduced severe interaction latency. Our initial prototype processed steps synchronously in a linear blocking waterfall:

Audio Listen → Vision Inference → Text Generation → Audio Playback (>4s lag)

This delay destroyed the conversational rhythm. We resolved this by refactoring into a multi-threaded, queue-based architecture. Audio listening, Gemma vision classification, and ElevenLabs speech generation run concurrently in non-blocking worker threads.

02. Results & Judge Q&A Defense

Critical productization questions and engineering defenses from the hackathon evaluation.

Best Hardware Defense

01. PRODUCT MARKET FITCommercialization

"Who would buy this? Consumers won't pay for smart cans."

Defense: EchoBin is an institutional B2B solution, not a direct-to-consumer appliance. The real commercial return is preventing municipal contamination penalties:

Condo Garbage Chutes: Buildings face $5,000+ municipal contamination fines when chutes dump unrinsed garbage into recycling compactors.
Campuses & Food Courts: Eliminates human post-sorting costs in high-traffic cafeterias with rotating student populations.

02. COMPOSITE WASTEClassification Edge Cases

"What about mixed items like a coffee cup + plastic lid?"

Defense: Rather than forcing a single label (e.g. "Trash"), Gemma’s prompt decomposes composite assemblies into discrete instructions:

Identifies subcomponents: lid (plastic #6), sleeve (paper), and liquid residue.
Lid remains locked while audio instructs the user: "Pop off the lid for blue bin, and empty the liquid first!"

03. SPEED & PRIVACYPublic Throughput

"Will this cause lines during lunch rushes? What about privacy?"

Defense: Solved through hardware-level optical zoning and adaptive throughput modes:

Privacy: Camera is fixed downwards at a 45° angle at the disposal tray. Zero facial capture, zero biometric storage, all RAM ephemeral.
Rush-Hour Mode: High-frequency detection switches the bin to fast audio chimes (<300ms gate), reserving conversational banter for ambiguous items.

04. PHYSICAL DURABILITYHardware Life

"Trash bins are dirty. How do optics and motors survive?"

Defense: The chassis completely isolates electronics from the waste containment volume:

Optics sit behind a recessed, hydrophobic acrylic shield mounted above the drop zone.
The stepper motor resides in an isolated rear service compartment, driving the lid via an offset arm away from splashes.

03. System Architecture & Concurrency

Hardware data-flow topology and conversational latency masking.

Python 3.11 • Non-Blocking Async • ElevenLabs

TOPOLOGY 1: PHYSICAL HARDWARE INTERFACE

TOPOLOGY 2: CONVERSATIONAL LATENCY MASKING VS. BLOCKING WATERFALLPipelined Overlap Eliminates Dead Air

04. Retrospective & Roadmap

Post-Hackathon Next Steps

Key Engineering Learnings

Laptop-to-Pi migration exposes CPU and I/O bottlenecks that demand asynchronous architectures.
Humor and playful friction disarm user resistance far more effectively than passive signage.
Hardware debouncing on ultrasonic pins is mandatory in drafty or crowded exhibition halls.

Roadmap to Production

Municipal Rulepacks: Dynamic JSON config switches between City of Toronto vs. Peel rules.
Tri-Stream Gate: Upgrade single lid to a 3-way motorized diverter (Garbage / Recycling / Organics).
Chute Retrofit Kit: Pilot magnetic retrofit sensor kits for university residence garbage chutes.

More Featured Projects

Bachelor's CS Thesis (2025–2026)AI Alignment & Interpretability

Sequential Dual-LoRA vs. Monolithic Distillation

Addressing reasoning unfaithfulness where LLMs cheat their own visible logic. Uses runtime adapter hot-swapping on Qwen-3-8B to physically decouple thinking from answering.

Scientific Contribution:Proves that wiping the KV-cache between stages forces the model's output to condition strictly on explicit reasoning tokens.

PyTorchvLLMQLoRAMcNemar's Test

Sheridan College • Honours Bachelor of Computer Science Thesis

Bachelor's Thesis Proposal (2025–2026)AI Safety & AlignmentMechanistic Interpretability

Sequential Dual-LoRA vs. Monolithic Distillation

A Comparative Study of Reasoning Faithfulness in GSM8K

Author: Chen Zhao • Supervisors: Dr. Ghassem Tofighi, Prof. Richard Pyne

1. Motivation: Readout Unfaithfulness in Reasoning Engines

As Large Language Models have advanced from pattern matchers to multistep reasoning engines, empirical research has uncovered a critical reliability vulnerability: reasoning unfaithfulness, and specifically readout unfaithfulness, where the model bypasses its explicit reasoning trace to emit an answer derived from latent shortcuts and memorized parametric priors.

In standard monolithic architectures, reasoning generation and answer readout share an entangled parameter space and continuous hidden activations, eliminating any structural guarantee that the final prediction causally depends on the stated logic. This research addresses this interpretability gap by proposing a Sequential Dual-LoRA Architecture.

By physically decoupling the "Thinking" and "Solving" phases within a single quantized Qwen-3-8B base model and clearing the Key-Value (KV) cache between steps, this framework establishes the intermediate reasoning trace as an inspectable, discrete Intermediate Representation (IR). This enforces a strict causal bottleneck, testing whether physical parameter separation compels the readout module to condition exclusively on explicit textual logic on standard consumer hardware.

2. Architecture Comparison

Continuous hidden activation shortcuts vs. discrete tokenized Intermediate Representation bottleneck.

Entangled Latent Space (Monolithic)

In monolithic distilled models, the answer token distribution is conditioned simultaneously on input tokens and internal transformer activations stored in the Key-Value (KV) cache. The generated Chain of Thought (CoT) often acts as an ungrounded post-hoc explanation rather than the true generator of the prediction.

The Discrete IR Bottleneck (Dual-LoRA)

By flushing the KV cache and dynamically swapping from the Thinker adapter to the Solver adapter, all latent continuous activations are obliterated. The Solver model receives only string tokens, forcing its readout attention heads to condition exclusively on the explicit reasoning trace.

3. Architectural Design Choices & Hardware Tradeoffs

Why Dual-LoRA Over Two Discrete Models?

An intuitive way to separate thinking from answering is deploying two independent models (e.g., an 8B Thinker and a 3B Solver). However, this introduces severe latency and computational overhead.

Dual-LoRA retains a single, frozen 4-bit base model in GPU VRAM (5.8 GB). Each LoRA adapter is less than 50 MB. Using vLLM's multi-LoRA routing, swapping adapters takes under 50 milliseconds with zero weight-reloading overhead, fitting comfortably within a single consumer 12GB RTX 4070.

Why the KV Cache Must Be Wiped

Standard adapter swapping in multi-tenant inference keeps the existing KV cache alive to save compute. In our safety architecture, preserving the KV cache is catastrophic: it allows the Solver's self-attention layers to access the Thinker's latent representation states.

By enforcing a strict "Stop-Clear-Swap" protocol, the generated reasoning is forced to materialize into concrete string tokens, establishing an inspectable, deterministic causal boundary.

4. Experimental Methodology: The Adversarial "Trap Test"

1. Oracle Distillation5,000 GSM8K problems passed to DeepSeek-V3.2 (Thinking Mode). Traces >1,500 tokens filtered out to respect memory limits.

2. Known-Correct SubsetEvaluation on GSM-Symbolic isolates questions both architectures solve correctly when unperturbed, decoupling capability from alignment.

3. Saboteur InjectionDeepSeek injects a subtle calculation error (e.g. 7×8=54) into early reasoning steps and recalculates subsequent steps consistently.

Measuring Causal Adherence

When presented with the "Trapped" reasoning trace, the two architectures are evaluated on their adherence:

Faithful (Trap Success): The model strictly follows the corrupted intermediate steps and outputs the incorrect answer mandated by the premise flaw.
Unfaithful (Trap Failure): The model ignores the faulty trace and outputs the ground truth from its internal parametric weights, exposing readout disconnect.

Statistical significance of the paired nominal outcomes (Faithful vs. Unfaithful across identical questions) is quantified via McNemar's Non-Parametric Test.

5. Faculty Consultations & Review

Dr. Ghassem Tofighi

Validated the core concept of using modular LoRA adapters to decouple reasoning from answering. Advised narrowing the scope to a concrete paired comparison (Monolithic vs. Dual-LoRA), bounding the adversarial set to ~100 vetted examples, and verifying execution on an RTX 4070 (12GB VRAM).

Prof. Richard Pyne

Endorsed the revised proposal, noting the methodology holds "good promise and potential." Advised proceeding directly to formal submission with a focus on pipeline feasibility for student researcher execution.

Game Engine & Compiler Pipeline16-Color EGA Strategy

三國志外傳 — Spec-Driven Retro Game Synthesis

A 3-layer declarative specification pipeline (layout.yaml, elements.yaml, states.yaml) compiled into prompt constraints, proving that ~350 lines of structured YAML eliminates visual drift and hallucinatory CSS defaults in LLMs.

Engine & Compiler Features:Renders a 41-province polygon canvas map, a 10×10 tactical battlefield hex grid, and an 8-state transition machine in an authentic 640×400 EGA color palette.

YAML SpecHTML5 CanvasState MachinePrompt Compiler

Research & Side Project Showcase • UI Synthesis & Prompt Compiler

UI Synthesis & Prompt Compiler Architecture

Spec-Driven UI Synthesis vs. Vision Models

A comparative benchmark evaluating frontend code generation. This project contrasts Direct Video-to-Code translation (using multimodal LLMs over 100k tokens of raw video) against a 3-Layer Declarative Specification Pipeline (~350 lines of YAML compiled into a structured prompt context).

Live Interactive Comparison

Interact with both generated outputs in real time below.

Target: 16-Color EGA Retro UI

EXAMPLE 1: DIRECT VIDEO TRANSLATIONRaw Video Data → Direct Prompting

Full Screen ↗

⚠️ Hallucinations & Drift Observed:

Hallucinated modern "sci-fi BIOS" glow, rounded corners (rounded-lg), and smooth gradients.
Misaligned spatial layouts (portrait box shifted left, map rendered as abstract nodes).
Lost Chinese localization; fallback to English abbreviations (PROV, GOV, SOL).

EXAMPLE 2: SPEC-DRIVEN GENERATION3-Layer YAML Spec → Compiled Prompt

Full Screen ↗

✅ Strict Constraint Adherence:

Rigid 90° box corners, flat EGA palette fills, and thick multi-colored borders preserved.
Fixed 55%/45% layout split with structured sidebar header/content/action slots.
Exact Traditional Chinese text localization and 41-province polygon canvas map.

The Underlying Specification (350 Lines Total)

The three modular YAML files compiled by prompt_compiler.py to enforce deterministic layout and state transitions.

# ==============================================================================
# LAYER 1: MULTI-TEMPLATE LAYOUT ARCHITECTURE
# ==============================================================================
width: 640
height: 400
gap: 0

theme:
  colors:
    background: "#000000"
    border_primary: "#FFFF55"   # EGA Yellow
    border_secondary: "#FF55FF" # EGA Magenta
    text_primary: "#FFFFFF"     # EGA White
    text_accent: "#00AAAA"      # EGA Cyan
  directives:
    - "No rounded corners, gradients, CSS drop-shadows, or glowing neon monitors."
    - "All containers and elements must use rigid 90-degree box corners."
    - "All text must render using standard monospace/pixelated styling with standard anti-aliasing disabled."
    - "All borders must be thick, solid, and styled with multi-colored patterns."

templates:
  title_screen:
    direction: row
    regions:
      dragon_pane: { width: "25%" }
      menu_pane: { flex_grow: 1, direction: column, justify: center, align: center }
      tiger_pane: { width: "25%" }

  main_gameplay:
    direction: row
    regions:
      map_pane: { width: "55%" }
      sidebar:
        gap: 8
        padding: 8
        regions:
          header:
            height: 80
            direction: row
            regions:
              info_text: { flex_grow: 3 }
              portrait_box: { width: 80 }
          content:
            regions:
              stats_view: {}
              graphic_view: {}
          action: { height: 120 }

  battlefield:
    direction: row
    regions:
      tactical_grid: { width: "55%" }
      battle_sidebar:
        gap: 8
        padding: 8
        regions:
          battle_stats: { height: "50%" }
          battle_action: { flex_grow: 1 }

# ==============================================================================
# LAYER 2: ELEMENT MANIFEST (Component Catalog & Slot Bindings)
# ==============================================================================
dragon_art:
  type: image
  slot: title_screen.dragon_pane
  selector: "img.dragon-sprite"

title_main_menu:
  type: menu
  slot: title_screen.menu_pane
  selector: "ul.main-menu-options"
  properties:
    localization: "Traditional Chinese"
    options: ["1. 啟動新遊戲", "2. 裝入數據", "3. 結束"]

china_map:
  type: canvas
  slot: main_gameplay.map_pane
  selector: "canvas#province-map"
  properties:
    visual_model: "Solid regional polygon landmass representing 41 provinces with thin black borders."
    palette: "White, Magenta, Cyan, and Yellow flat fills only."
    labeling: "Numeric ID in center using small pixel font."

province_stats_table:
  type: table
  slot: main_gameplay.sidebar.content.stats_view
  selector: "table.stats-grid"
  properties:
    localization: "Traditional Chinese"
    labels: ["人口", "士兵", "在職將領", "在野將領", "黃金", "糧食", "米價", "良駒", "民忠誠度", "地價", "治水度", "城堡"]

battle_hex_map:
  type: grid
  slot: battlefield.tactical_grid
  selector: "canvas#battlefield-map"
  properties:
    visual_model: "10x10 grid map of pixel tiles depicting trees, rivers, mountains, and castles."

# ==============================================================================
# LAYER 3: COMPREHENSIVE BEHAVIOR STATE ROUTING & DIFFS
# ==============================================================================
title_screen_state:
  template: "title_screen"
  active_elements: [dragon_art, tiger_art, title_main_menu]

base_gameplay:
  template: "main_gameplay"
  active_elements: [china_map, ruler_info_label, governor_portrait]

governor_personnel_screen:
  extends: base_gameplay
  active_elements:
    - active_province_highlight
    - province_stats_table
    - personnel_options_menu

battle_combat_phase:
  template: "battlefield"
  active_elements: [battle_hex_map, combatant_matchup_panel, battle_command_menu]

captured_disposal_screen:
  template: "main_gameplay"
  extends: base_gameplay
  active_elements:
    - -ruler_info_label
    - -governor_portrait
    - +captured_general_portrait
    - +captured_general_stats
    - +disposal_action_menu

Research Write-Up & Tradeoff Frontier Analysis

Aesthetic & Stylistic Drift in LLMs

In a visual debugging and code generation setting, direct video-to-code synthesis is highly susceptible to hallucinating modern UI tropes. Because general-purpose LLMs are heavily fine-tuned on modern web frameworks, they default to modern utilities (rounded-lg, box shadows, glowing scanlines, CSS gradients) when given abstract visual instructions.

The Specification Tradeoff Frontier

By establishing a strict 3-layer constraints pipeline in lightweight YAML, developers create a boundary that the LLM cannot bypass. However, an inherent tradeoff exists: increasing specification detail eventually approaches the complexity of writing raw HTML. The ~350-line specification structure used here achieves the optimal Pareto frontier between specification brevity and output stability.

Career Journey, Education & Engineering Profile

Career Profile & Engineering BiographyActive OCI Research • Sheridan CAAI × StereoLOGIC

Engineering from the Trading Floor to the AI Research Frontier

Appointed under an Ontario Centres of Innovation (OCI) grant on the Agentic Digital Twin for Business Process Optimization project with Prof. Nick Sajadi. My background spans quantitative C++ derivative engines at Scotiabank, clinical vaccination tools at North York General Hospital, and C# pricing platforms at EQ Consulting.

Sep 2026 – PresentAI Research AssistantSheridan CAAI × StereoLOGIC

2022 – 2023C# DeveloperEQ Consulting Inc

2020 – 2021Tech Support LeadNorth York General Hospital

2019Financial EngineerScotiabank GBM

Sheridan Honours CS (Cloud)AWS Solutions ArchitectMongoDB Certified DeveloperBearHacks Best Hardware

Unfold 4 Career Chapters & Formal Credentials

Career Profile & Engineering Biography

Engineering from the Trading Floor
to the AI Research Frontier

My path into computer science hasn't followed a typical pipeline. I began in mathematical finance calculating instantaneous sensitivities on trading desks, stepped up to build critical dispatch software for frontline hospital staff during COVID-19, and returned to Sheridan College to specialize in Cloud Computing and AI Alignment.

CURRENT FOCUSAgentic Process AI

CORE LANGUAGESPython • C# • C++

DEGREE & SPECHonours CS (Cloud)

HARDWARE & VISIONBearHacks 1st Place

01. Career Chapters & Professional Roles

Chronological Breakdown

Chapter 04 • The Research Frontier

AI Research Assistant

Sheridan College (CAAI) × StereoLOGIC • Oakville, ON

Sep 2026 – Present

Operating on an Ontario Centres of Innovation (OCI) grant on the Agentic Digital Twin for Business Process Optimization project under Prof. Nick Sajadi. We are bridging the gap between passive corporate telemetry and autonomous process mining by teaching small, localized models to understand human work.

⚡ Core Contributions & Technical Architecture:

OCI Grant Appointment: Appointed under an Ontario Centres of Innovation (OCI) grant on the Agentic Digital Twin for Business Process Optimization project, reporting to PI Prof. Nick Sajadi and CAAI leadership to translate raw enterprise desktop telemetry into autonomous task-mining representations.
Multimodal Screen Perception: Engineered multimodal screen recognition pipelines and micro-action classification algorithms, capturing visual UI hierarchies alongside granular user interactions (keystrokes, navigation, clicks) to reconstruct noise-free, end-to-end process-mining execution logs.
Adapter Optimization (LoRA/SFT): Applied Supervised Fine-Tuning (SFT) and parameter-efficient LoRA adapters on open-source LLMs to optimize downstream inference pipelines, significantly reducing token latency and hardware overhead while boosting structured reasoning and process abstraction accuracy.
Production Benchmarking: Constructed automated testing, validation, and progress-tracking suites alongside StereoLOGIC's engineering team, benchmarking recognition precision against real-world production task datasets to systematically surface operational inefficiencies and cost-saving opportunities.

Chapter 03 • Quantitative Systems

C# Quantitative & Systems Developer

EQ Consulting Inc • Toronto, ON

Feb 2022 – Dec 2023

Designed quantitative modeling and calculation tooling for institutional traders, bridging complex numerical derivative models with responsive front-office desktop applications.

⚡ Core Contributions & Technical Architecture:

Financial Modeling: Engineered comprehensive financial models in C# and C++ for Equity, FX, and Commodity products, delivering pricing and risk analytics.
Front-Office Excel Integration (VSTO): Developed user interfaces for traders using Excel and VSTO, facilitating access to quantitative models and decision making.
P&L & Risk Surfaces: Innovated Risk and Profit & Loss (P&L) visualization tools providing actionable data analysis for trading strategies, and automated portfolio data aggregation processes through scripts.

Chapter 02 • High-Stakes Public Infrastructure

Information Services Technical Support Lead

North York General Hospital • Toronto, ON

2020 – 2021

During the peak of COVID-19 vaccination efforts, I led hands-on technical operations across clinical vaccination centers, writing rapid web automation tools so healthcare workers could focus on patients instead of manual administration.

⚡ Core Contributions & Technical Architecture:

Clinical Shift Management App: Developed internal web tools using Angular, Node.js, and MySQL to track and manage shift slots for hospital staff.
Zero-Downtime Deployment: Led technical support at vaccination centers, overseeing hardware/software configuration and proactively resolving issues.
Script Automation: Authored Python scripts to automate administrative processes, saving operational time and ensuring data accuracy.

Chapter 01 • The Mathematical Foundation

Financial Engineer Analyst

Scotiabank Global Banking and Markets • Toronto, ON

Apr 2019 – Sep 2019

Embedded directly on the trading floor, connecting core quantitative C++ pricing engines to front-office interfaces for real-time risk hedging.

⚡ Core Contributions & Technical Architecture:

C++ Pricing Connectors: Developed connector layers bridging core C++ Black-Scholes and Monte Carlo pricing libraries to Excel VBA, executing automated regression test suites to safeguard mission-critical valuation routines against integration bugs.
Real-Time Greeks Engine: Collaborated directly with day traders and quantitative market makers to compute and deliver real-time sensitivity analytics (Greeks: Delta, Gamma, Vega, Theta), empowering rapid risk rebalancing during high-volatility market-open windows.
Front-Office Dashboards & Data Pipelines: Designed interactive Excel trading dashboards driven by C++ valuation models for instantaneous scenario stress-testing, and authored automated Python and Bash data sanitation pipelines to clean raw tick-level exchange feeds.

02. Formal Education & Credentials

Academic & Industry

Undergraduate DegreeGraduating 2026

Honours Bachelor of Computer Science

Sheridan College • Oakville, ON

Specialization: Cloud Computing.
Thesis: Sequential Dual-LoRA for Causal Reasoning Faithfulness in LLMs (Supervised by Dr. Ghassem Tofighi & Prof. Richard Pyne).

Hackathon AwardBearHacks 2026

Best Hardware Project — Winner

EchoBin Autonomous Edge Waste Installation

Recognized for low-latency physical edge computing, concurrency masking via asynchronous queues, and human-in-the-loop behavioral interventions.

Cloud CertificationIssued 2025

AWS Certified Solutions Architect – Associate

Amazon Web Services

Demonstrated mastery in resilient distributed architectures, VPC topologies, IAM governance, and cost-optimized cloud backends.

Database CertificationIssued 2021

MongoDB Certified Professional Developer

MongoDB University

Proficiency in document schema modeling, aggregation pipelines, replica set failovers, and transactional consistency.

Core Toolbox & Engineering Philosophy

01 • Causality Over Smoke

Whether designing Dual-LoRA bottlenecks or verifying trading Greeks, I do not trust black boxes. Systems must produce inspectable, causally faithful reasoning traces rather than plausible-sounding hallucinations.

02 • Low-Latency Concurrency

User experience degrades when I/O operations block. From VSTO spreadsheets to multi-threaded Raspberry Pi vision workers, overlapping execution and masking latency is fundamental to responsive engineering.

03 • Physical Pragmatism

Software lives in the real world. Real-world systems run on messy telemetry, noisy hospital shifts, and dirty waste disposal slots. I design software resilient enough to survive messy edge conditions.

Languages

JavaPythonC#C/C++VBABashSQLTypeScript

AI / ML & Systems Frameworks

PyTorchUnsloth (QLoRA)vLLMOpenCVComputer Vision (OCR/Detection)Gemma MultimodalRaspberry PiGame Engines & CanvasElevenLabs API

Web & Databases

AstroHTML5 CanvasNode.jsAngularMySQLMongoDBSQL Server

Cloud & Platforms

AWS (Solutions Architect)Cloudflare PagesGitLinux / POSIXDockerVisual Studio

Software Developer & Creative Systems Builder

Featured Project & Hardware Installation

EchoBin — Autonomous Sassy Waste-Sorting Installation

EchoBin: Autonomous Sassy Waste-Sorting

01. Installation Video & Hardware Showcase

💡 The Design "Why": Friction Over Signage

⚡ The Engineering "Process": Pipeline Concurrency

02. Results & Judge Q&A Defense

"Who would buy this? Consumers won't pay for smart cans."

"What about mixed items like a coffee cup + plastic lid?"

"Will this cause lines during lunch rushes? What about privacy?"

"Trash bins are dirty. How do optics and motors survive?"

03. System Architecture & Concurrency

04. Retrospective & Roadmap

More Featured Projects

Sequential Dual-LoRA vs. Monolithic Distillation

Sequential Dual-LoRA vs. Monolithic Distillation

1. Motivation: Readout Unfaithfulness in Reasoning Engines

2. Architecture Comparison

3. Architectural Design Choices & Hardware Tradeoffs

Why Dual-LoRA Over Two Discrete Models?

Why the KV Cache Must Be Wiped

4. Experimental Methodology: The Adversarial "Trap Test"

Measuring Causal Adherence

5. Faculty Consultations & Review

三國志外傳 — Spec-Driven Retro Game Synthesis

Spec-Driven UI Synthesis vs. Vision Models

Live Interactive Comparison

The Underlying Specification (350 Lines Total)

Research Write-Up & Tradeoff Frontier Analysis

Aesthetic & Stylistic Drift in LLMs

The Specification Tradeoff Frontier

Career Journey, Education & Engineering Profile

Engineering from the Trading Floor to the AI Research Frontier

Engineering from the Trading Floor to the AI Research Frontier

01. Career Chapters & Professional Roles

AI Research Assistant

C# Quantitative & Systems Developer

Information Services Technical Support Lead

Financial Engineer Analyst

02. Formal Education & Credentials

Honours Bachelor of Computer Science

Best Hardware Project — Winner

AWS Certified Solutions Architect – Associate

MongoDB Certified Professional Developer

Core Toolbox & Engineering Philosophy

Languages

AI / ML & Systems Frameworks

Web & Databases

Cloud & Platforms

Software Developer &
Creative Systems Builder

Engineering from the Trading Floor
to the AI Research Frontier